1. Field of the Invention
This invention relates to a computer system, and more particularly to a computer architecture that integrates multiple systems within a system. The computer architecture allows systems to remain fully operational and updated as to control status of peripheral and input output devices. The systems remain fully operational, capable of processing and performing complete functions, even while another system has control over the peripheral or input output devices.
2. Description of the Related Art
Computer architectures can incorporate multiple computer systems with system having its own central processing unit and memory. The systems, however, share common peripherals such as a display and input output devices such as keyboards, mice, and disk drives. In some cases the computer systems utilize the same type of processor, allowing application programs and files to be shared between systems. In these computer architectures one computer system controls the common devices and directly interfaces to a user while the other system or systems, in a less than optimal manner, processes or computes in the background. In other cases the computer architecture may use dissimilar computing systems. One computing system may have certain advantages over the other system that the user desires to make use of. At other times the user may desire to take advantage of the features of the other computer system.
Regardless of the number of computer systems that are employed, typically computer architectures provide for one set of registers with each register assigned to a particular commonly shared peripheral or input output (IO) device. For example, a floppy disk drive (FDD) register is assigned to the floppy disk drive. This information contained in the register provides address and access content to the CPU or CPUs. In a multiple system computer architecture, when a particular computer system has control over the commonly shared devices, the set of registers is accessed by the CPU of that computer system in control of the shared devices. The other system or systems are isolated from the registers.
When a system and its CPU are isolated from the registers, whenever that system receives control over the common devices that system must also be able to access the registers. Typically, a reset to the system and CPU is needed. Alternatively, the CPU can be placed in a suspend or sleep state. This is particular true for CPUs that comply with the advanced configuration and power interface (ACPI) specification. The ACPI specification is an open industry specification which establishes industry-standard interfaces for operating system (OS) directed configuration and power management for computing systems such as personal computers, namely desktop and notebook computers.
The ACPI specification enables new power management technology to evolve independently in OS and hardware and ensures that they continue to work together. An ACPI-compatible OS can balance processor performance against power consumption and thermal states by manipulating the processor clock speed and cooling controls.
Suspend or sleep states are provided by the ACPI specification. Sleep states are used to help minimize system power consumption, manage system thermal limits, and maximize system battery life. Power management involves tradeoffs among system speed, noise, processing speed, battery life, and alternating current power consumption. The following are sleep states for a CPU, as defined by the ACPI specification. The xe2x80x9cS0xe2x80x9d state is a full running state in which the CPU is on and fully operative. The xe2x80x9cS1xe2x80x9d state is a sleep state with low wake-up latency. In xe2x80x9cS1xe2x80x9d state, no computer system context is lost and the system hardware maintains all system context. The xe2x80x9cS2xe2x80x9d state is also a low wake-up latency sleeping state. xe2x80x9cS2xe2x80x9d state is similar to the xe2x80x9cS1xe2x80x9d state except the CPU and system cache context is lost; the OS is responsible for maintaining the caches and the CPU context. The xe2x80x9cS3xe2x80x9d sleep state is a low wake-up latency sleeping state where all system context is lost except system memory. In the xe2x80x9cS3xe2x80x9d state, CPU, cache, and chip set context are lost, and hardware maintains memory context. The xe2x80x9cS4xe2x80x9d sleep state is the lowest power, longest wake-up latency sleeping state defined by the ACPI specification. In the xe2x80x9cS4xe2x80x9d state, in order to reduce power to a minimum, the hardware platform powers off all devices, while platform context is maintained. The xe2x80x9cS5xe2x80x9d state is the xe2x80x9coffxe2x80x9d state. The xe2x80x9cS5xe2x80x9d state places the system in the xe2x80x9csoftxe2x80x9d off state and requires a complete boot when awakened.
In computer architectures with multiple systems and using one set of registers the following is true for processors or CPUs that follow the ACPI specification. The family of Intel Pentium(copyright)based processors in particular follow the ACPI specification and is used as an example. In a computer architecture that uses an Intel Pentium(copyright)based processor, a single set of registers is provided. The registers identify the devices, control status, and availability to the processor. The processor continuously looks at the registers to determine the peripheral or IO devices that are available. In an architecture with multiple, and in particular dual, computing systems, when one system has control of the peripherals or IO devices, the other system with an Intel Pentium(copyright)processor should be placed in a sleep state. Otherwise, if the Intel Pentium(copyright)processor is allowed to continue operating at full capability, the Intel Pentium(copyright)processor will continuously look for the registers. The Intel Pentium(copyright)processor should be placed in an xe2x80x9cS3,xe2x80x9d xe2x80x9cS4,xe2x80x9d or xe2x80x9cS5xe2x80x9d state so that it is not running or will not be able to run. Considering that the highest operating state, xe2x80x9cS3,xe2x80x9d only allows the processor to maintain system memory and system context is lost, the isolated Intel Pentium(copyright)processor based system that does not control the common peripherals and IO devices essentially is turned off. Processing for the isolated Intel Pentium(copyright)based system is essentially discontinued, while another system is in control.
Now referring to FIG. 1, illustrated is a computing architecture with two computing systems. In this example two dissimilar computing systems are used in the computer architecture. Both systems share common peripheral and IO devices. Illustrated are a PC-based system 100 and a personal digital assistant (PDA) based system 105. The PC system 100 is connected to quick switch 115 by a low pin count (LPC) bus 120. The quick switch 115 can isolate the PC system 100 from the PDA system 105, and allows either system to control a common set of peripherals or IO devices 135. In this example, the PC system 100 can be looked as a xe2x80x9cmasterxe2x80x9d device and the PDA system 105 looked as a xe2x80x9cslavexe2x80x9d device. When the PDA system 105, however, is in control of the common peripheral or IO devices 135, the PC system 100 is isolated from the peripheral or IO devices 135 and the device registers. The quick switch 115 connects the PDA system 105 by a LPC bus 125. The LPC bus 125, the quick switch 115, and the LPC bus 120 combine to connect the PC system 100 to a super input output embedded controller 110 (SIO EC). The SIO EC 110 is connected to the quick switch 115 and the PDA system 105 by LPC bus 125. The PC system 100 isolation control is provided from the quick switch 115 to SIO EC 110 represented by multiplexor control bus 130. The SIO EC 110 is the interface to a set of commonly shared peripheral or IO devices 135. Within the SIO EC registers assigned to the particular peripheral or IO devices may reside. Whenever either the PC system 100 or the PDA system 105 control the peripheral or IO devices 135, the other system cannot access the registers. In the event the PC system 100 is isolated, it must discontinue processing and placed in an appropriate ACPI sleep state.
A need has been felt for a computing architecture and method that allows a computer system to continue full processing and computing operations while another system has control over commonly shared peripherals and IO devices. This architecture and method would provide maximum processing capability for the multiple systems in the computer architecture, allow continuous processing and computing, and avoid the need to reset or place in a suspend state any or all of the processors.
The aforementioned and other features are accomplished, according to the present invention, by providing a dedicated set of registers to each computing system in a multiple system computing architecture. A computing system that must continuously look for register information is allowed to continue full computing operations since it will always have access to required registers.
An embedded controller is provided to allow access for a computer system in control to commonly shared peripheral or IO devices. A switch isolates computer systems that are not in control at a particular moment. The switch also isolates registers from other systems in order not to confuse particular computer systems.
Since each computing system has certain requirements as to which peripherals are needed to have access to, the dedicated registers may be modified by enabling, disabling or elimination. Each register will have access to a particular device or port related to a device.